Dual damascene (DD) patterning is a technique for forming interconnect structures in integrated circuits (ICs) using conductive copper metal lines. The copper metal lines may be inlaid into an oxide or low-k dielectric layer by plating the metal into preformed trenches. Chemical mechanical polishing may then be performed to remove excess metal from the wafer surface.
Via-first DD patterning is a DD process in which via fill material may be used to minimize the resist thickness variations in the trench patterning step. The via-first approach to DD patterning may require high etch selectivity between the interlevel dielectric (ILD) and etch stop layer (ESL), substrate reflectivity control, and thorough removal of post-etch residues. A siloxane-based material referred to as SLAM (Sacrificial Light-Absorbing Material) satisfies many of these requirements. SLAM features a comparable dry etch rate to many ILDs, good etch selectivity to photoresists (or “resists”), high absorption of light at exposure wavelengths, and compatibility with standard lithographic processes.
Current SLAM materials may be formulated to be compatible with silicon oxide-based ILD materials in both etch rate and cleanability. These silicon-oxide materials are typically more difficult to remove than resists, and may require more aggressive chemical or thermal processing. Consequently, harsh processing conditions (thermal and/or chemical) may be required in SLAM-assisted DD patterning to remove the SLAM and resists.